Small electronic devices such as integrated circuits (IC's) are prone to damage and failure from electro-static-discharges (ESD). ESD failures may occur in the factory and contribute to lower yields. Various ESD-protection structures have been placed near input, output, or bi-directional I/O pins of ICs. Many of these protection structures use passive components such as series resistors, diodes, and thick-oxide transistors. Other ESD structures use an active transistor to safely shunt ESD current.
As manufacturing ability improves and device sizes shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are much more susceptible to over-voltage failure but can operate with a lower power-supply voltage and thus consume less power and produce less heat.
Such smaller transistors are often placed in an internal “core” of an IC, while larger transistors with gate lengths that are above the minimum are placed around the core in the periphery. ESD-protection structures are placed in the periphery using these larger transistors. Some mixed-voltage chips may have two cores, each operating with a different power-supply voltage. Larger transistors may be used in a high-voltage core that uses a higher power-supply voltage, while smaller transistors may be used in a low-voltage core that uses a lower power-supply voltage.
Although internal nodes of the smaller core transistors do not connect directly with Input-Output pads of the IC, the inventor has realized that parts of ESD pulses may be capacitively coupled to internal core transistors, causing unexpected damage in the core, despite ESD-protection structures in the periphery.
Thinner gate oxides of the core transistors can be shorted, and substrate junctions melted by relatively small capacitively-coupled currents applied to the tiny core devices. Static charges from a person or machinery can produce such damaging currents that are only partially blocked by the input-protection circuits in the periphery.
Mixed-voltage chips such as a System-On-a-Chip (SOC) are often used in certain applications. These mixed-voltage chips have both high-voltage core circuitry 10 and low-voltage core circuitry 20.
FIG. 1 is a prior-art mixed-voltage chip with an ESD-protection clamp. High-voltage core circuitry 10 contains core transistors 12, 14, which have a larger channel length but can still be damaged by voltages that were considered normal voltages a few years ago. High-voltage core circuitry 10 receives a higher power supply voltage VDDH.
Low-voltage core circuitry 20 contains core transistors 22, 24, which have a small channel length and can be damaged by relatively low voltages. Low-voltage core circuitry 20 receives a reduced power supply voltage VDDL, such as from a voltage regulator that steps down an external power supply VDD to a voltage that can be safely applied to core transistors 22, 24 and other transistors in low-voltage core circuitry 20. For example, VDDH may be 5 volts and VDDL may be 3 volts, or VDDH may be 3 volts and VDDL is 1.8 volts, 1.2 volts, or some other value. As device sizes shrink, VDDH may be 1.8 volts and VDDL may be 1.2 volts. There may be thousands of core transistors in high-voltage core circuitry 10 and in low-voltage core circuitry 20.
Protection from ESD pulses may be provided on each I/O pad, and by mixed-voltage power clamp 16. Mixed-voltage power clamp 16 is coupled between VDDH and ground (VSS), and shunts current from an ESD pulse between the power rails.
Some cross-domain coupling occurs between high-voltage core circuitry 10 and low-voltage core circuitry 20, such as through substrates and capacitances. An ESD pulse applied to high-voltage core circuitry 10 may be coupled into low-voltage core circuitry 20 by this cross-domain coupling, causing damage to transistors 22, 24 in low-voltage core circuitry 20. Mixed-voltage power clamp 16 may shunt enough current from the ESD pulse to reduce such cross-domain coupling to prevent damage. ESD pulses applied to I/O pins may still couple into high-voltage core circuitry 10 or into low-voltage core circuitry 20, such as through power lines, but mixed-voltage power clamp 16 may then be activated to reduce potential damage. Mixed-voltage power clamp 16 may also turn on for other ESD pulses such as those applied to I/O pins, when the ESD pulse is shunted through a diode in the I/O pin's ESD-protection structure to the internal VDDH rail, causing an indirect VDDH-to-VSS ESD pulse.
FIG. 2 is a graph of I-V characteristics of high-voltage transistors used in high-voltage core circuitry 10 and of low-voltage transistors used in low-voltage core circuitry 20. As a pulse such as an ESD pulse is applied to a low-voltage transistor such as is used in low-voltage core circuitry 20, the low-voltage transistor is turned off so the current is low as the voltage rises from the origin, as shown for curve 90.
Once the voltage is above the avalanche breakdown voltage VT1L, at current IT1L, drain-to-source breakdown occurs (avalanche breakdown of the parasitic NPN transistor in an n-channel transistor). The current then increases dramatically as the voltage is reduced (snaps back) as current flow continues to increase until the current reached the holding current IR at the holding voltage, VH. This holding voltage VH must be above the power-supply voltage VDDH to prevent latch-up.
As more current is applied to the transistor at the holding voltage, the current rises quickly until the second threshold voltage VTL2 is reached, at current ITL2. Then thermal breakdown occurs as portions of the transistor may melt or otherwise be permanently damaged.
Curve 92 is similar in shape to curve 90, but has higher voltage thresholds for snap-back or avalanche breakdown, since curve 92 is for high-voltage transistor that are used in high-voltage core circuitry 10. The high-voltage transistor reached snap-back threshold voltage VT1H before the transistors in high-voltage core circuitry 10 break down, as shown by the dashed line, but after low-voltage transistors in low-voltage core circuitry 20 break down, as shown by the LV-Core Breaks vertical line. Thus high-voltage transistors are not effective in protecting low-voltage transistors in low-voltage core circuitry 20. However, using a low-voltage transistor to protect high-voltage core circuitry 10 may cause latch-up problems since holding voltage VH is below the high-voltage power supply VDDH.
Low-voltage transistors may be used in ESD protection circuits for low-voltage core circuitry 20, while high-voltage transistors may be used in ESD protection circuits for high-voltage core circuitry 10. However, because of cross-domain coupling, an ESD pulse may still cause damage. It is difficult to protect both power domains with a single circuit, since breakdown voltages are different for high- and low-voltage transistors. In particular, power clamps, which provide ESD protection between power and ground, are difficult to design to operate with both power domains. A low snap-back voltage is needed to protect the low-voltage transistors, but a high holding voltage is needed to prevent latch-up of the low-voltage transistors to the high-voltage power supply.
What is desired is an electro-static-discharge (ESD) protection circuit that can protect against damage from ESD pulses for both high-voltage cores and low-voltage cores. An improved ESD power clamp circuit for a mixed-voltage chip with two cores is desirable. An ESD clamp that protects both high-voltage core transistors and low-voltage core transistors without causing latch-up is desirable. An ESD power clamp with a low snap-back voltage and a high effective holding voltage is desirable.